RISC-V CPU Microarchitecture / RTL
$100,000–$500,000 year
Remote · Santa Clara, California, United States or US
Job Summary
RISC-V CPU Unit Microarchitecture Specification and RTL Design for next-generation CPU. Defines and develops microarchitecture specifications for units (branch predictor, rename, instruction scheduling, vector execution, load/store, vector load/store support), including analysis/strategy for verification and PPA closure. Responsible for RTL design quality, verification environment, and RTL optimization to control PPA. Applies AI-assisted design adaptation and may mentor junior engineers. Qualifications include Bachelor's/Master's/PhD in EE/CE/CS, proven CPU RTL design experience across RISC-V (and/or x86/Arm/POWER/SPARC), deep verification strategy knowledge, CPU microarchitecture understanding, V-extension preferred, HDL proficiency (Verilog/SystemVerilog/VHDL), strong problem-solving, communication, and collaboration skills.
Required Qualifications
- Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field
- Proven track record of designing high-performance CPU RTL for x86, Arm, POWER, SPARC, or RISC-V
- Deep understanding of design verification strategy and trade-offs for verification methodology (simulation, formal, various checkers, etc...)
- Deep understanding of CPU microarchitecture and PPA trade-off
- Basic understanding of RISC-V Architecture including V-extension is preferred
- Proficiency in hardware description languages (HDLs) such as Verilog, SystemVerilog or VHDL
- Excellent problem-solving abilities and analytical skills
- Strong communication skills, with the ability to convey complex technical concepts to diverse audiences
- Ability to work collaboratively in a team-oriented environment and across multiple disciplines
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