RAN Validation Engineer
On-siteHyderabad, Telangana, India
Job Summary
Develop and maintain SystemVerilog/UVM-based verification environments for FPGA block-level and top-level designs. Create directed-random test scenarios, assertions, and functional coverage while performing simulation-based verification using industry-standard tools. Drive debug and root-cause analysis of functional issues, integrate VIPs and scoreboards, and support FPGA bring-up and validation on evaluation boards. Review RTL and test plans to ensure quality, mentor junior engineers, and lead regression runs and coverage closure. This role requires 4–8 years of experience and familiarity with Xcelium, Vivado, and high-speed interfaces.
Required Qualifications
- 4–8 years of hands-on experience in functional verification
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
- Strong hands-on expertise in SystemVerilog
- Strong hands-on expertise in UVM
- Experience with hardware/software co-verification
- Knowledge of high-speed interfaces (AXI, AXI‐Stream, DDR, SPI)
- Strong analytical and debugging skills
- Ability to work effectively in cross-functional teams
- Excellent written and verbal communication skills
- Self-driven with the ability to own verification tasks end-to-end
- High attention to detail and commitment to quality
- Working knowledge of Verilog
- Working knowledge of VHDL
- Experience with Xcelium
- Experience with Questa
- Experience with VCS
- Experience with Xilinx Vivado
- Experience with SimVision
- Experience with Python
- Experience with Tcl
- Experience with Shell
- Experience with Git
- Ability to work in a standard office environment
- Ability to use a computer for extended periods
- Occasional lab work for FPGA bring-up and debug
Desired Qualifications
- Familiarity with cadence tools like Xcelium
- Familiarity with Xilinx Vivado
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