Quantum Superconducting Interconnect Integration Engineer

Lead development of superconducting interconnect and interposer integration processes for quantum packaging, including 2.5D and 3D cryogenic interposer architectures; define routing, metallization, and integration schemes optimized for low-loss RF/microwave signal propagation and minimal thermal leakage; own end-to-end integration across wafer-level processes (RDL, TSV/TOV, via formation) and die-level interfaces (bump, bonding, assembly); architect multi-die quantum packaging solutions (qubit die + control electronics, superconducting interposers) and enable chiplet-style/system-level integration; translate system-level requirements into interconnect density, pitch, and routing specifications; enable early-stage prototyping, maintain manufacturability and cost considerations; collaborate with device, test, OSATs, suppliers, and research partners to preserve qubit performance and meet cryogenic constraints; mentor and guide new hires; contribute to IP/publications and report progress to stakeholders; travel up to 20% as needed.