PRINICPAL RTL DESIGN
On-siteBoise, Idaho, United States
Job Summary
Own and drive RTL design for DRAM digital and mixed-signal IP from specification through silicon-ready signoff. Architect and deliver high-performance, power- and area-efficient RTL designs aligned with product requirements. Perform and sign off front-end quality checks, including lint, CDC/RDC, synthesis, UPF, and timing QoR. Collaborate closely with physical design, verification, and architecture teams to achieve timing closure and PPA goals. Improve design quality and efficiency by refining methodologies, driving automation, and enhancing RTL design flows. This role offers strong opportunities for technical leadership and innovation across global teams in Boise, Idaho.
Required Qualifications
- Master's degree in Electrical Engineering
- 8+ years of experience
- Bachelor's degree with 10+ years of pre-silicon RTL design experience
- Proven ownership of complex RTL/IP development from micro-architecture definition through handoff to physical design
- Strong experience with ASIC low-power design methodologies, including UPF-based power intent and power-aware CDC/RDC
- In-depth knowledge of RTL design, logic synthesis, functional verification, and static timing analysis (STA)
- Proficiency in Verilog/SystemVerilog and industry-standard simulation and front-end tools
- Must be available for Boise, Idaho
Desired Qualifications
- Extensive background in DRAM or other memory compose architectures and development
- Deep knowledge of CDC, RDC, STA, and low-power techniques in advanced ASIC technology nodes
- Experience designing complex digital logic and/or mixed-signal-interfacing circuits
- Familiarity with CMOS digital and analog-integrated circuit concepts and their system-level impact
- Excellent interpersonal skills with the ability to influence multi-functional teams and technical leadership
Hiring someone like this?
Get your role in front of qualified candidates on Sorce.