Principal/Staff Design Verification Engineer
On-sitePenang, Jawa Timur, Republic of Indonesia
Job Summary
Lead the verification strategy and execution for assigned Design Under Test (DUT) blocks, ensuring comprehensive functional coverage and high verification quality. Guide the verification team in developing test plans aligned with design specifications, while creating testbenches, test sequences, and stimulus scenarios to validate DUT functionality. Run simulations, debug RTL issues, and manage regression testing to ensure design stability. Develop automation scripts and Verification IP to improve team productivity, and maintain clear documentation including coverage reports and sign-off readiness. Collaborate cross-functionally with design and architecture teams to resolve issues and achieve project milestones.
Required Qualifications
- At least 10 years of relevant experience in IC/SoC functional verification
- Strong debugging skills with RTL simulation and waveform analysis tools
- Proficient in UVM, SystemVerilog, Verilog, and SVA languages
- Strong knowledge in protocols such as AXI, NoC, RISC-V
- Proven ability to lead verification efforts and mentor engineers
- Excellent team player with strong communication skills
- Excellent communication and collaboration skills in cross-functional development environments
Desired Qualifications
- Bachelor's degree or above in Microelectronics, Semiconductor Engineering, Electronic & Electrical Engineering, or related fields
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