Principal Software Integration Engineer
$133,200–$185,000 year
On-siteSan Jose, California, United States
Job Summary
Own RTL design for assigned blocks from microarchitecture through synthesis sign-off, developing high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA. Drive design reviews, lint, CDC, and timing closure activities to silicon-ready quality while partnering with architecture, verification, and physical design teams to translate specifications into implementation-ready microarchitecture. Collaborate on testplans, coverage closure, bug triage, and scan, BIST, and floorplanning to support aggressive tapeout schedules. Debug complex pre-silicon and post-silicon issues across RTL, gate-level, and emulation environments. Mentor junior engineers and contribute to design methodology, scripts, and best practices to scale with the roadmap.
Required Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
- 5+ years of digital design experience, including at least one full chip from spec to tapeout
- Strong proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows
- Hands-on experience with timing closure, CDC, lint, and low-power design techniques
- Solid understanding of high-speed serial interfaces (PCIe, Ethernet, or similar) and SoC integration
Desired Qualifications
- MS or PhD in Electrical Engineering or Computer Engineering
- Experience with PCIe Gen5/Gen6, CXL, UALink, UCIe, or Ethernet MAC/PCS designs
- Familiarity with formal verification, emulation, or assertion-based methodologies
- Background in advanced process nodes (7nm, 5nm, or below)
- Strong debug skills across pre-silicon and post-silicon environments
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