Principal SoC RTL Engineer
On-site · Austin, Texas, United States
Austin, Texas, United StatesOn-siteFull TimeSenior LevelBachelors DegreeSmall
Type
Full Time
Level
Senior Level
Education
Bachelors Degree
Company size
Small
Job Summary
Principal RTL Engineer to own pre-tapeout quality for digital SoC modules on MCU platforms; develop Verilog/SystemVerilog RTL for complex IPs/SoCs, evaluate/integrate 3rd-party IP, collaborate with verification, FPGA, physical design teams to hit timing/power targets, and drive RTL quality, LINT, CDC, RDC, silicon bring-up, and validation. Requires Bachelor's in a related field and ~20 years of experience with SOC/IP design, architecture, verification planning, and hands-on RTL development.
Required Qualifications
- Bachelor’s degree in Electronics Engineering, Electrical Engineering, Instrumentation & Control Engineering, or related field
- 20 years of experience in SOC/SoC design or related field
- Deep knowledge of current and emerging SOC design technologies
- Expert knowledge in designing, implementing, and troubleshooting IPs and SoCs
- Ability to estimate impact and lead implementations across technical areas
- Architectural and program leadership across technical areas
- Ability to collaborate with verification, FPGA, and physical design teams
- Experience with Verilog/SystemVerilog RTL development
- Experience with pre-tapeout quality for digital SOC modules
- Experience with LINT, CDC, RDC checks and silicon bring-up
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