Principal SoC Physical Implementation/STA Engineer
On-siteBengaluru, Karnataka, India
Job Summary
Lead a team of STA engineers and drive timing closure for advanced SoC designs across multiple technology nodes. Create, validate, and maintain Synopsys Design Constraints (SDC) for block and full-chip levels, then perform exhaustive timing analysis across process, voltage, and temperature variations. Debug and resolve setup, hold, transition, and path-based violations by generating and evaluating Engineering Change Orders. Partner with Architects, Front End, DFT, and PD teams to understand design requirements, develop multi-mode timing constraints, and refine timing models. Develop and support implementation flows using industry-standard EDA tools while improving script-based automation.
Required Qualifications
- 12+ years of experience doing STA for SoCs and Blocks
- experience of Multi mode timing constraint development, execution, and final timing signoff for advanced technology nodes
- Create, validate, and maintain Synopsys Design Constraints (SDC) for block and full-chip levels, covering false paths, multicycle paths, and test modes
- Perform exhaustive timing analysis across multiple corners and modes (MCMM), adhering to process, voltage, and temperature (PVT) variations
- Debug and resolve setup, hold, transition, and path-based violations (PBA)
- Drive timing closure by generating and evaluating timing Engineering Change Orders (ECOs)
- Partner with RTL, physical design, and DFT teams to ensure robust timing integration and refine timing models
- Develop and support implementation flows using industry-standard Electronic Design Automation (EDA) tools
- improve script-based automation
- Debugging timing issues from GLS
- lead the writing constraints and closing timing activities
- Drive a team of STA engineers
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