Principal SoC I/O Performance Architect
HybridVancouver, British Columbia, Canada
Job Summary
Define performance objectives, analysis methods, and signoff criteria for SoC I/O subsystems, including bandwidth, latency, QoS, and congestion. Build and apply performance models to evaluate architectural options early, then analyze data from simulations, emulation, firmware tests, traces, and counters to correlate pre-silicon predictions against RTL and post-silicon results. Create reusable workloads, synthetic traffic patterns, and benchmark flows while developing automation and AI-assisted workflows to accelerate sweeps and triage. Partner with architecture, design, DV, emulation, firmware, software, and platform teams to communicate tradeoffs and drive design decisions through evidence-based recommendations. This role shapes performance strategy from early concepts through silicon and into platforms.
Required Qualifications
- Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline—or equivalent practical experience
- Familiarity with high-performance I/O, interconnect, memory, and coherency technologies such as PCIe, CXL, IOMMU/SMMU, UALink, Ethernet, InfiniBand, NVLink, UCIe, AXI, CHI, coherent fabrics, or DMA engines
- Hands-on experience building or using performance models—analytical, event-driven, or transaction-level—with C++, Python, or SystemC/TLM
- Comfort working with performance data from simulation, emulation, firmware/software tests, traces, counters, benchmarks, and silicon debug tools
- Demonstrated technical leadership, cross-team influence, and a track record of using performance evidence to shape product or silicon direction
Hiring someone like this?
Get your role in front of qualified candidates on Sorce.