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NXP SemiconductorsPosted 3 weeks ago

Principal SoC Chip Lead

On-siteShanghai, Shanghai, China or Tianjin, Tianjin, China

Full TimeSenior LevelBachelors DegreeEnterprise

Job Summary

Own SoC program execution from project definition through tape-out and post-silicon support, ensuring on-time delivery of key milestones and coordinating engineering support during silicon bring-up and validation. Drive technical decision-making across architecture, integration, verification, implementation, and system teams while resolving dependencies and critical project risks. Lead cross-functional alignment among RTL, DFT, Physical Design, and IP teams, developing execution plans with PMO to monitor schedules and drive recovery actions when milestones are at risk. Partner with Product Marketing, System Engineering, and external stakeholders to communicate status and mitigation plans during management reviews. Own overall tape-out readiness and coordinate post-silicon validation activities to support issue resolution.

Required Qualifications

  • Bachelor's degree or higher in Microelectronics, Electrical Engineering, or related disciplines
  • 6+ years of semiconductor industry experience
  • Proven experience in SoC development from architecture through tape-out
  • Strong understanding of SoC development flows including: Architecture, RTL Design, Integration, Verification, DFT, Emulation, Physical Design, Silicon Validation
  • Experience leading large cross-functional engineering teams
  • Strong project execution, planning, and risk management skills
  • Excellent communication, leadership, and stakeholder management capabilities
  • Ability to influence technical direction and drive execution in a matrix organization

Desired Qualifications

  • Previous experience as: Chip Lead / SoC Technical Lead / Chief Engineer / Project Technical Leader
  • Experience with automotive, industrial, or safety-critical semiconductor products
  • Experience working with global development teams across multiple sites
  • Successful delivery of multiple SoC tape-outs and post-silicon product ramps

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