Principal Signal and Power Integrity Engineer.

Senior SI/PI Engineer responsible for modeling, simulating, and validating high-speed and high-power electrical performance across advanced multi-die packages and system interconnects. Key responsibilities include pre- and post-layout SI simulations (eye diagrams, crosstalk, insertion/return loss) for UCIe, D2D, SerDes, and Ethernet links; PDN modeling and decoupling strategy; building and validating S-parameter, IBIS-AMI, and behavioral models for packages, PCBs, sockets, and cables; guiding PCB/package layout teams on stack-ups, routing constraints, and return-path continuity; bring-up and measurement validation (VNA/TDR, oscilloscope) and correlating hardware results with simulations; cross-functional collaboration with IC design, packaging, and board teams to define electrical requirements and debug issues; evaluating new SI/PI methodologies and emerging interconnect technologies; and leading end-to-end electrical validation for next-generation AI compute systems.