Principal RTL Design Engineer
$180,000–$255,000 year
On-siteSan Jose, California, United States
Job Summary
Own microarchitecture and RTL implementation for a major block or subsystem of the Reconfigurable Dataflow Unit, from specification through tape-out. Define and document specifications for complex digital blocks in compute, memory, or on-chip network subsystems. Write, integrate, and debug synthesizable SystemVerilog RTL through the full chip lifecycle. Hit aggressive frequency targets via datapath pipelining and microarchitectural restructuring. Own PPA trade-offs and drive timing closure with physical design, synthesis, and STA. Enforce quality gates including lint, CDC, and LEC. Partner with verification to define intent and support debug. Work with architects and software teams to prototype performance features and drive AI/automation into the design flow. Set the technical bar in reviews and mentor engineers.
Required Qualifications
- BS or MS in EE, CE, or CS with 7+ years (or equivalent) of industry experience in ASIC RTL design
- Mastery of synthesizable SystemVerilog for high-speed, high-performance ASICs, including SVA to capture design intent
- High-frequency design experience: datapath pipelining, retiming, critical-path restructuring, and other microarchitectural techniques for hitting aggressive frequency targets
- Deep foundation in computer architecture and digital logic design: arbitration, flow control, clock domain crossing, and memory structures
- Ownership of a complex block or subsystem from microarchitecture specification through tape-out on at least one production ASIC
- Physical-design awareness: converging power, performance, and area against real physical constraints, including floorplan, congestion, and timing feedback from the physical design team
- Hands-on experience with synthesis and static timing analysis, and with lint, CDC, and LEC quality flows
- Demonstrated technical leadership without formal authority: setting direction in design reviews, arbitrating microarchitecture decisions, and mentoring engineers
- Scripting in Python for design and flow automation
Desired Qualifications
- Depth in one RDU domain: compute and dataflow datapath, on-chip network and interconnect, or memory subsystem
- Industry-standard interconnects and protocols: AXI, PCIe, Ethernet, HBM/DDR
- AI and ML workload acceleration techniques, and dataflow or reconfigurable architectures
- Formal property checking applied to design intent
- Advanced TSMC nodes and multi-die or chiplet design
- Performance modeling and analysis to support architectural trade-offs
- Fluency with Claude or other AI tools applied to RTL design and flow development
- MS or PhD in EE, CE, or CS with 10+ years of experience in ASIC RTL design
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