Principal Physical verification Engineer
On-site · Bengaluru, Karnataka, India
Job Summary
Own full-chip physical verification signoff for complex ASIC/SoC designs, including DRC, LVS, ERC, PERC and antenna/ESD checks; drive tape-out readiness, converge violations, and deliver clean GDS. Develop and maintain PV flows and scripts (Calibre/ICV), define and enhance reliability rule checks (ESD, EOS, current-density constraints), lead floorplanning and power-grid planning to minimize PV iterations, debug complex PV violations, and collaborate with CAD teams and foundries/vendors while mentoring junior and senior engineers.
Required Qualifications
- Bachelor’s or Master’s degree in Electrical/Electronics Engineering or related field
- Typically 10–15+ years of experience in physical verification for complex ASIC/SoC designs
- Proven experience owning DRC/LVS/PERC signoff for at least one 5 nm (or sub-7 nm) production tape-out in a FinFET process
- Hands-on experience with industry-standard PV tools (e.g., Siemens Calibre, Synopsys IC Validator) for DRC, LVS, ERC, PERC and ANT/ESD checks
- Cadence Virtuoso-PV tool integration (Virtuoso layout to Caliber/ICV)
- Strong scripting skills in Python, Perl, Tcl, or Unix shell for automation
- Experience with PERC-based reliability flows for ESD, EOS, LUP and current-density-based checks
- Familiarity with DFM/DFY checks, density/fill strategies, and pattern-matching-driven rule decks
- Solid understanding of physical design (place & route, timing closure, power integrity) and its interaction with PV signoff
- Excellent problem-solving and communication skills
- Ability to mentor and lead cross-functional teams and interface with foundry/EDA vendors
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