Principal Physical Design Engineer, Methodology
$185,000–$240,000 year
On-siteSan Jose, California, United States
Job Summary
Define, develop, and maintain reusable physical design flows spanning synthesis, place-and-route, extraction, STA, and EMIR for complex SoCs at advanced nodes. Own the end-to-end RTL-to-GDSII flow infrastructure across multi-vendor toolchains including Cadence Innovus, Tempus, Voltus, Pegasus, and Synopsys Fusion Compiler, ICC2, and PrimeTime. Evaluate and qualify new tool features to continuously improve PPA and schedule predictability while integrating DRC/LVS/extraction runsets. Build automation scripts to manage large-scale multi-corner STA and EMIR runs and develop QoR optimization frameworks. Establish best practices, runset standards, and quality checks that scale across multiple concurrent tapeout programs. Support physical design engineers with flow issues, tool configurations, and methodology guidance. Drive adoption of flow improvements across the team through training and documentation. This fully on-site role at Astera Labs' San Jose location requires 8+ years of experience and expert-level scripting in Python, Tcl, and Perl.
Required Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
- 8+ years of experience in physical design methodology, CAD, or flow development for complex SoCs at advanced nodes (7nm and below)
- Strong knowledge of synthesis, place-and-route, extraction, STA, and equivalence checking flows
- Experience with both Cadence (Innovus, Tempus, Voltus, Pegasus) and Synopsys (Fusion Compiler, PrimeTime, StarRC, ICC2) toolchains
- Expert-level scripting ability in Python, Tcl, and/or Perl for flow development and automation
- Experience building and maintaining multi-corner/multi-mode analysis infrastructure
- Understanding of foundry design rules, technology files, and enablement kit integration
- Ability to work independently with strong prioritization and a results-driven mindset
- This role is fully on-site at our San Jose, CA location
Desired Qualifications
- Masters Preferred
- Knowledge of agentic AI solutions for EDA automation
- Experience with CI/CD integration for physical design flows
- Familiarity with compute farm management and job scheduling optimization
- Knowledge of advanced packaging or multi-die integration flows
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