Principal Physical Design Engineer
$174,000–$352,500 year
On-site · Sunnyvale, California, United States
Job Summary
Lead Physical Design for ASICs focusing on RTL-to-GDS flow development using Innovus and Fusion Compiler. Develop robust floorplanning, placement, CTS, routing, timing closure, IR/EM mitigation, and DRC/LVS signoff processes; automate workflows with Tcl, Python, and Make; collaborate with RTL, analog/mixed-signal, and PD teams to deliver high-performance silicon; drive tool-feature evaluation and technology bring-up for next-generation nodes; ensure best-in-class timing, area, power, and signoff quality.
Required Qualifications
- BS/MS in Electrical Engineering, Computer Engineering, or related field
- 7–10+ years of experience in ASIC physical design flows or physical design methodology
- Strong expertise in Cadence Innovus place and route and/or Synopsys Fusion Compiler
- Physical design fundamentals (floorplan, placement, CTS, routing, ECO flows)
- Timing concepts (setup/hold closure, OCV/AOCV/POCV, derates)
- Power/thermal integrity (IR drop, EM reliability)
- DRC/LVS and physical signoff flows
- Strong scripting skills in Tcl, Python, and Linux shell
- Ability to troubleshoot complex tool, flow, or methodology issues across PD and signoff
- Experience with advanced process nodes (7 nm, 5 nm, or below) is preferred
- Familiarity with UPF/low-power flows, multi-clock-domain designs, and hierarchical P&R
- Experience with version control systems (Git/Perforce) and CI automation
- Knowledge of extraction, STA signoff, and parasitic modeling (StarRC, PrimeTime)
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