Principal PCIe Logic Design
$108,300–$201,100 year
HybridHillsboro, Oregon, United States
Hillsboro, Oregon, United StatesHybridFull Time$108,300–$201,100 yearSenior LevelDoctorate Or Professional DegreeMedium
Full TimeSenior LevelDoctorate Or Professional DegreeMedium
Job Summary
Contribute to the architecture and micro-architecture of next generation PCIe IP and implement these designs in System Verilog. Collaborate with the verification team to verify the IPs and participate in prototyping of the IPs in cutting edge FPGAs. Also contribute to support of existing generations of the IPs. This full-time position targets the latest developments in PCIe standards and involves working closely with local teams as well as with multi-cultural, multi-national colleagues. The role requires an average of at least three days per week onsite, allowing for two days of remote work.
Required Qualifications
- RTL coding: Verilog / System Verilog
- Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent
- 8+ years of experience with RTL Design
- Good English skills
- communication skills
- willingness to work with an international team
Desired Qualifications
- Knowledge of PCIe / CXL
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