Principal Packaging Engineer
$180,000–$240,000 year
Remote · Palo Alto, California, United States
Job Summary
Senior-level Principal Packaging Engineer responsible for architecting and delivering advanced multi-die IC packages for high-performance AI accelerators. This role focuses on package architecture, substrate design, manufacturability, and vendor engagement. Responsibilities include selecting and designing optimal multi-die package types (MCM, 2.5D, 3D, fan-out, CoWoS, InFO, CPC, CPO), defining substrate stack-ups and routing, high-speed signal escaping and power distribution network design, managing subcontractors and coordinating with TSMC/OSAT, partnering with IC design, physical design, SI/PI, and board teams to meet system-level needs, evaluating emerging packaging technologies, and supporting package bring-up, failure analysis, debug, and qualification.
Required Qualifications
- B.S./M.S. in Electrical Engineering or related field
- Experience with multi-die package design and UCIe integration
- Understanding of substrate materials, stack-ups, and mechanical constraints
- Familiarity with SI/PI concepts to collaborate with electrical teams
- Experience managing packaging subcontractors
- Experience interfacing with TSMC/OSAT for bumping and packaging options
- Knowledge of package modeling tools (HFSS, Sigrity, or similar) is a plus
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