Principal NoC IP Micro-Architect
$209,500–$299,200 year
On-siteSan Jose, California, United States
San Jose, California, United StatesOn-siteFull Time$209,500–$299,200 yearSenior LevelLarge
Full TimeSenior LevelLarge
Job Summary
Develop end-to-end architecture, RTL design, and simulation for scalable Network on Chip IP solutions integrated into Altera's next-generation FPGA platforms. Lead the definition of microarchitecture features, create logic diagrams, and deliver software models for device-level bring-up while optimizing for power, performance, and area. Guide the NOC team through verification plans, resolve failing RTL tests, and apply automation to ensure high-quality IP development. This highly visible technical leadership role requires deep expertise in SoC interconnects and system-level optimization.
Required Qualifications
- Bachelor's or Master's Degree in Electrical Engineering, Computer Engineering, or a related field
- 15+ years of related working experience
- 10 + years of experience in System Verilog, VCS/Synopsys simulators, Lint and Synthesis
- 10+ years of experience in programming with C/C++/Perl/Python/TCL/Unix Shell script
Desired Qualifications
- 10+ years of experience in FPGA design and programming
- 10+ years of experience in RTL validation
- 10+ years of experience in development of Network on Chip IPs
- 5+ years of experience with the usage of AI with development process for high efficiency development
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