Principal Mixed Signal Design Verification, Team Lead
On-siteMusselburgh, Scotland, United Kingdom
Job Summary
Lead the Mixed Signal Verification team for next-generation Power ICs, including Motor Drivers and PMICs, by defining end-to-end verification strategy from initial architecture to tape-out sign-off. Architect scalable SystemVerilog/UVM testbenches and drive the integration of AI-driven automation tools to streamline global flows. Translate system requirements into automated tests while enforcing ISO 26262 Hardware Safety standards and analog/digital boundaries. Mentor engineers in behavioral modeling for analog blocks and manage regression metrics using GitLab to ensure functional and code coverage closure. Partner with design teams on pre-design feasibility studies and contribute to top-down chip architecture definitions.
Required Qualifications
- Bachelor's or Master's degree in Electrical Engineering, Microelectronics, or a highly related technical field
- 8+ years of hands-on experience in Mixed-Signal Design Verification (MSDV)
- 4+ years of proven leadership experience, directly managing or leading verification teams through complex tape-out cycles
- Expertise in SystemVerilog, SVA (Assertions), and UVM methodologies
- Proficiency in scripting languages (e.g., Python, Bash, Perl) to drive automation and efficiency
- Strong familiarity with Cadence mixed-signal simulation environments
- Deep understanding of analog and mixed-signal blocks to guide the team in writing high-fidelity behavioral models (PLLs, Charge Pumps, Bandgaps, etc.)
Desired Qualifications
- Strong background in power-related topologies (Motor Drivers, PMICs, Gate Drivers) is highly preferred
Hiring someone like this?
Get your role in front of qualified candidates on Sorce.