Principal, Mask Design Engineer
On-site · Tokyo, Tokyo, Japan
Job Summary
Principal, Mask Design Engineer responsible for GaN power-device layout, ensuring high-quality, high-yield layouts, leading layout tooling improvements, and coordinating with design and layout teams. Must-have: BS in EE (preferred), 8+ years in semiconductor layout, Cadence Virtuoso/Layout XL/Calibre/Unix, understanding of electrical properties; nice-to-have: L-edit, power-discrete device layout. Role requires layout verification (LVS/DRC/ERC), tape-out management, reticle/mask generation, foundry communication, and development of new workflows; hybrid remote option with Tokyo office.
Required Qualifications
- BS ( EE major preferred)
- At least 8 years’ experience in semiconductor layout
- familiarity with Cadence Virtuoso
- Layout XL
- Calibre
- Unix
- Understanding of basic electrical properties
- Knowledge in the integrated circuit electronics including device level cross section, analog and transistor level circuit is a big plus
- Good communication skills
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