Principal / Lead DSP & Systems Architect — Ultra High-Speed SerDes
On-siteMilpitas, California, United States
Job Summary
Define DSP and system architecture for 448G and post-448G SerDes IP, including ADC/DAC partitioning, modulation selection, and FEC strategy. Build MATLAB/Python models of full links across electrical and optical media, analyzing channel response, impairments, and FEC performance. Own the DSP pipeline from FFE to soft-decision FEC, driving mixed-signal co-design for ADC/DACs and optimizing fixed-point implementations for power and area. Generate block-level specs for datapaths and align decisions across digital, analog, and packaging domains. Translate reference models into RTL with cycle-accurate alignment, partnering with verification teams. Partner with validation to correlate post-silicon results with modeled assumptions and debug methodologies. Guide DSP and systems engineers while developing reusable models and contributing to IP innovation strategy.
Required Qualifications
- Graduate degree in EE, Communications, or Signal Processing
- 10+ years in high-speed SerDes or wireline/optical link DSP/systems architecture
- Direct exposure to 112G/224G silicon
- Clear path into 448G and beyond across electrical and optical interfaces
- Proven ownership of end-to-end link budgets with cascaded impairment analysis across channel (electrical and/or optical), AFE, ADC/DAC, DSP, and FEC
- Deep expertise in: PAM4/PAM6 and coherent wireline/optical signaling
- Advanced equalization (FFE, DFE, MLSE/MLSD, Tomlinson-Harashima)
- Optical DSP (CD/PMD compensation, polarization recovery, carrier phase/frequency recovery)
- Adaptive algorithms and link training
- KP4 and soft-decision FEC
- High-speed ADC/DAC architectures (time-interleaved, calibration, ENOB-driven design)
- CDR and timing recovery at multi-hundred-Gbaud rates
- Jitter/crosstalk/SI and optical impairment modeling
- Fixed-point DSP and bit-true modeling
- MATLAB/Python link simulation
- DSP-to-RTL methodology
- Familiarity with OIF CEI (CEI-224G, CEI-448G), IEEE 802.3 high-speed Ethernet, and relevant optical standards (e.g., OIF coherent agreements, IEEE 802.3 optical PHYs)
- Track record of defining specs consumed by RTL, DSP, mixed-signal, verification, and validation teams
- Strong communication skills with VP- and CTO-level stakeholders at hyperscale and module customers
Desired Qualifications
- PhD
- Optical exposure
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