Principal Hardware Application Engineer
On-siteTaipei, Taiwan, Taiwan
Job Summary
Lead customer design engagements as the primary hardware technical focal for strategic accounts, driving design-in activities from schematic review through board bring-up and mass production. Review customer PCB schematics and layout files for Marvell DC switch platforms, providing guidance on component selection, power sequencing, and high-speed signal routing. Perform or coordinate signal integrity and power integrity simulations for 800G and 1.6T interfaces, evaluating channel performance and SerDes tuning. Support hardware bring-up at customer sites and the Taipei lab, debugging L1 issues including link training and thermal failures. Author design guides, application notes, and layout guidelines while collaborating with global engineering teams and supplier chain partners to optimize platform designs. Ramp knowledge on next-generation interconnect technologies including UALink, ESUN, and CPO.
Required Qualifications
- Bachelor's degree or above in Electrical Engineering, Electronics Engineering, or a related field
- 8+ years of experience in hardware design or hardware application engineering for high-speed networking or data center systems
- Proficiency in EE design tools: schematic capture (e.g., Cadence OrCAD, Mentor PADS, or equivalent) and PCB layout review (e.g., Cadence Allegro or equivalent)
- Solid knowledge of signal integrity (SI) principles for high-speed differential interfaces: understanding of channel loss, eye diagram analysis, SerDes Tx/Rx equalization, and PAM4 link budget
- Familiarity with power integrity (PI) concepts: PDN design, AC/DC simulation, decoupling strategy, and power sequencing
- Experience supporting customers through the hardware design cycle: schematic review, layout review, bring-up, and EDVT
- Strong communication skills — able to present technical findings clearly to both engineering teams and customer stakeholders
- Proactive, self-driven working style with the ability to manage multiple customer engagements in parallel
Desired Qualifications
- Hands-on experience with DC switch or high-speed Ethernet platforms (e.g., 400G, 800G, 1.6T switch designs)
- Familiarity with Marvell Teralynx (TL7, TL10, T100) or equivalent DC switch silicon
- Experience with SI/PI simulation tools (e.g., Sigrity, Ansys SIwave, HFSS, PowerDC or equivalent)
- Knowledge of next-generation interconnect technologies: UALink, ESUN, CPO, or 224G SerDes
- Knowledge with thermal design considerations for high-power switching platforms (air cooling, liquid cooling)
- Familiarity with MSDC (Microsoft, AWS, Google, Meta) ODM design requirements and supply chain ecosystem in Taiwan
- Experience with board bring-up tools: oscilloscopes, VNAs, BERT, and real-time sampling scopes
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