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Silvus Technologies8 months ago

Principal FPGA / RTL Design Engineer - Signal Processing

$165,000–$250,000 year

On-site · Irvine, California, United States

Type
Full Time
Level
Senior Level
Education
Bachelors Degree
Company size
Unknown
Industry
Technology

Job Summary

Principal FPGA / RTL Design Engineer focused on signal processing for Silvus' MIMO wireless networking products. Responsibilities include system-engineering collaboration, RTL coding and simulation, FPGA synthesis and timing closure, hardware verification, and supporting RF and software teams. Requires extensive RTL/FPGA experience, Verilog/SystemVerilog expertise, Xilinx FPGA/Vivado proficiency, and a strong background in fixed-point DSP for wireless communications. Onsite role in Irvine, CA with standard office environment expectations and the potential for field-testing support.

Required Qualifications

  • Bachelor of Science degree in Electrical Engineering, Computer Science, or related fields
  • Minimum 10 years of demonstrated experience in RTL design and FPGA implementation
  • 8 years of RTL design and FPGA implementation with an advanced degree (MS or PhD) in Electrical Engineering, Computer Science, or related fields
  • Demonstrated experience with fixed point binary arithmetic and digital signal processing (DSP) designs
  • Deep knowledge of RTL design fundamentals using Verilog and System-Verilog
  • Proven expertise working with front-end RTL design tools, FPGA synthesis, timing closure, multiple clock-domain and/or high-utilization FPGA designs
  • Experience with Xilinx FPGAs, SoCs, and the Vivado IDE
  • Must be a U.S. Citizen due to clients under U.S. government contracts
  • All employment is contingent upon the successful clearance of a background check and drug testing

Desired Qualifications

  • MS or PhD degree in Electrical Engineering, Computer Science, or relevant fields
  • Strong communication and presentation skills
  • Experience with wireless communication systems on FPGA or ASIC designs
  • Basic MATLAB skills
  • Solid knowledge and understanding of scripting languages such as Perl and Python

Additional Requirements

  • Must be a U.S. Citizen due to clients under U.S. government contracts
  • Background check and drug testing required
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$165k – $250k / yr

Principal FPGA / RTL Design Engineer - Signal Processing · Silvus Technologies

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