Principal Engineer, SOC Integration
$219,000–$351,000 year
On-siteSan Jose, California, United States
Job Summary
Own the integration of SoCs with multiple high-speed interfaces, including ARM cores, DDR controllers, and UCIe PHYs. Review third-party IPs and integrate them with system buses, peripherals, and CPU cores while collaborating with architects and verification engineers to ensure sound design. Partner with physical designers on timing constraints, synthesis, DFT insertion, and static timing analysis to develop prototype and production controllers. This role focuses on enhancing memory and storage capabilities within Samsung's DRAM Development Lab to support emerging machine learning and edge computing applications.
Required Qualifications
- BS in Computer/Electrical Engineering or Computer Science with 20+ years of experience
- MS with 18+ years of experience
- Hands on knowledge & experience in ASIC design flow from design to tape out
- Experience in the commercial IPs such as UCIe, CPU, Ethernet, and DDR interfaces
- Good understanding of PPA (performance, power, and area) trade-offs
- Experience in SoC level synthesis, timing analysis, lint check, CDC checks
- Good knowledge and experience in AMBA bus fabric, ARM CPU cores and ARM Co-sight debug features
- Daily onsite presence at our San Jose office/headquarters
Desired Qualifications
- Self-motivated problem-solver with an ability to work well in a team
- You're inclusive, adapting your style to the situation and diverse global norms of our people
- An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding
- You're collaborative, building relationships, humbly offering support and openly welcoming approaches
- Innovative and creative, you proactively explore new ideas and adapt quickly to change
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