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Samsung Austin Semiconductor3 months ago

Principal Engineer, SOC Design

$219,000–$351,000 year

On-site · San Jose, California, United States or Folsom, California, United States

Type
Full Time
Level
Senior Level
Education
Doctorate Or Professional Degree
Company size
Enterprise
Industry
Semiconductor

Job Summary

Lead architect for SOC design within Samsung's DRAM Development Lab, focusing on development of silicon solutions and architectural definitions for subsystem and chip-level designs. Responsibilities include top integration, RTL implementation, quality checks (Assertion, Lint, CDC, STA), reviewing 3rd party IPs (ARM cores, DDR controller, UCIe PHY), integrating IPs and subsystems at the SoC level, coordinating with architects and verification engineers on design soundness, and working with physical designers on timing constraints, synthesis, DFT insertion, and static timing analysis. Requires extensive hands-on ASIC design experience, IP experience (UCIe, CPU, Ethernet, DDR), strong PPA trade-off knowledge, and ability to operate across design-to-tapeout workflows; travel and collaboration with cross-functional teams are implied within a global R&D environment. The role supports a senior-level engineer with a strong track record in SoC-level synthesis, timing, lint, and CDC checks, and emphasizes collaboration, inclusivity, continuous learning, and adaptability within Samsung’s innovation-driven culture.

Required Qualifications

  • Bachelors in Electrical, Computer Science or related with 20+ years of experience or Masters in Electrical, Computer Science or related Science with 18+ years of Industry Experience or PhD in Electrical, Computer Science or related Science with 15+ years of Industry experience preferred
  • Hands on knowledge & experience in ASIC design flow from design to tape out
  • Experience & Good knowledge in ATE vector generation, testing and silicon bring up
  • Experience in the commercial IPs such as UCIe, CPU, Ethernet, and DDR interfaces
  • Good understanding of PPA (performance, power, and area) trade-offs
  • Experience in SoC level synthesis, timing analysis, lint check, CDC checks
  • Experience in interfacing 3rd party service companies for DFT/PI/PD
  • Good knowledge and experience in AMBA bus fabric, ARM cores
  • Self-motivated problem-solver with an ability to work well in a team
  • You’re inclusive, adapting your style to the situation and diverse global norms of our people
  • An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding
  • You’re collaborative, building relationships, humbly offering support and openly welcoming approaches
  • Innovative and creative, you proactively explore new ideas and adapt quickly to change
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$219k – $351k / yr

Principal Engineer, SOC Design · Samsung Austin Semiconductor

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