Principal Engineer, Silicon Validation
$200,000–$255,000 year
On-site · San Jose, California, United States
Job Summary
Lead the silicon validation of Ayar Labs’ optical chiplets from initial bring-up through block- and chip-level signoff, applying deep expertise in high-speed SerDes, photonic systems, and post-silicon validation to shape AI infrastructure. Define and implement comprehensive validation methodologies for electronic-photonic SoCs, oversee tape-out bring-up with firmware/design teams, validate SerDes interfaces and mixed-signal blocks using standard lab equipment, and drive rigorous targets, coverage, and signoff criteria. Provide technical leadership and mentorship to senior and junior validation engineers, produce high-quality validation reports and signoff packages, and ensure alignment with industry standards (IEEE, OIF, JEDEC) and evolving optical interconnect requirements. Strong emphasis on Python-based automation, test infrastructure, and cross-functional collaboration to deliver robust product performance documentation.
Required Qualifications
- Bachelor's degree in Electrical Engineering or related field with 10+ years of relevant industry experience, or Master's degree with 7+ years of experience
- Demonstrated leadership in post-silicon validation for complex SoCs or multi-chip packages, including first silicon bringup and full signoff
- Hands-on expertise with high-speed SerDes validation and characterization (NRZ and PAM-4) using equipment such as BERTs, oscilloscopes/DCAs, and network analyzers
- Strong proficiency in Python for lab automation, data analysis, and test infrastructure development
- Experience developing and owning validation test plans end-to-end
- Deep understanding of communication protocols and standards (Ethernet, PCIe, etc.)
- Excellent communication skills and ability to drive cross-functional technical alignment
- Familiarity with optical transceiver standards and co-packaged optics integration challenges
- Knowledge of high-speed standards: Ethernet (200G/400G/800G), PCIe Gen5/6, OIF CEI
- Experience driving NPI and transition from lab validation to manufacturing test
- MSEE or equivalent (preferred)
- Preferred: Optical transceiver standards familiarity
- Experience with NEP/validation signoff processes
- Strong mentorship and leadership capabilities
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