Principal Engineer, PD

As a leader in Physical Design, you will own and drive all phases of the backend implementation flow for complex SoCs, including chip-level partitioning, synthesis, floorplanning, placement, clock-tree synthesis, place-and-route, timing closure, power and noise analysis, IR/EM reliability, and full physical verification. You will mentor and manage a high-performing team of RTL-to-GDSII physical design engineers, set technical direction, enable growth, and ensure world-class execution. You will define and deliver ambitious PPA targets through innovation, scalable methodologies, and robust reuse strategies. Collaboration is central to this role—partner closely with cross-functional teams across DFT, packaging, hardware, program management, IP, and foundry engineering. You will also champion the development, rollout, and adoption of next-generation EDA tools, flows, and methodologies. Other Responsibilities include performing all activities safely and supporting Environmental, Health, Security requirements; and ensuring compliance with pre-employment conditions.