Principal Engineer - Memory Circuit Design Verification
On-site · Hyderabad, Telangana, India
Hyderabad, Telangana, IndiaOn-siteFull TimeSenior LevelMasters DegreeEnterprise
Type
Full Time
Level
Senior Level
Education
Masters Degree
Company size
Enterprise
Job Summary
Principal Engineer - Memory Circuit Design Verification responsible for defining and driving verification architecture and methodology for next-generation DDR designs, developing verification plans and coverage strategies, architecting UVM-based testbenches, guiding verification teams, and applying AI/ML techniques to improve verification efficiency, with collaboration across build teams, tool vendors, and automation initiatives.
Required Qualifications
- Bachelor’s/Master’s or PhD degree or equivalent experience in Electrical Engineering, Computer Engineering, or a related field
- 12+ years in Design Verification (experience with DDR/GDDR/DDR memory Verification preferred)
- Expert-level proficiency in SystemVerilog, UVM, and advanced verification methodologies
- Familiarity with AMS Co-Simulation and mixed-signal verification flows
- Hands-on experience with simulation, coverage analysis, and regression management
- Excellent problem-solving, debugging, and analytical skills
- Proven ability to lead verification teams and influence technical direction
- Exposure to Python/TCL/Perl scripting for automation
- Understanding of AI/ML concepts as applicable to verification
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