Principal Engineer - IP Verification
On-site · Noida, Uttar Pradesh, India
Job Summary
Lead end-to-end verification for IPs and Subsystems, drive adoption of advanced verification methodologies, own verification quality metrics, pursue a zero-defect mindset through coverage closure and defect prevention, analyze and improve verification flows, and collaborate with global cross-functional teams across Design, DFT, Architecture, and Validation. Must-haves include 10–15 years in IP/Subsystem verification, SystemVerilog/UVM and C/C++, Verilog/VHDL, experience with VCS/NCSim/ModelSim/Questa, testbench architecture, functional/performance validation, SVA/functional coverage, ARM cores, and AMBA protocols; preferred exposure to formal methods, emulation, and domain knowledge in automotive, graphics/vision accelerators, high-speed serial interfaces, or Ethernet.
Required Qualifications
- 10–15 years of hands-on experience in IP or Subsystem verification for complex, multi-million gate designs
- Strong expertise in HVLs such as SystemVerilog/UVM and proficiency in C/C++
- Solid understanding of HDLs such as Verilog/VHDL
- Experience with industry simulators such as VCS, NCSim, ModelSim, or Questa
- Strong experience in testbench architecture, development, debugging, and verification closure
- Proficiency in test planning, feature traceability, and functional/performance validation
- Strong knowledge of assertions (SVA), functional coverage, and regression management
- Solid understanding of microcontroller architectures (ARM cores) and interconnect protocols such as AHB, AXI, AMBA
- Experience in memory subsystems including SRAM, Flash, DDR, and memory controllers
- Exposure to formal verification methodologies and tools
- Experience with gate-level simulations and verification planning tools
- Exposure to emulation and pre-silicon validation environments
- Domain knowledge in automotive, graphics/vision accelerators, high-speed serial interfaces, or networking protocols such as Ethernet
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