Principal Engineer, Digital Verification and Emulation
$190,000–$250,000 year
On-site · San Jose, California, United States
Job Summary
Lead hardware-assisted verification and emulation bring-up for next-gen silicon photonic chip; build reusable verification environments using SystemVerilog-based testbenches and emulation-ready test infrastructure; develop real-number and mixed-signal models for analog/digital interface verification; collaborate with firmware/software for pre-silicon workloads and long-running system scenarios on emulation platforms; define verification plans, functional and code coverage, and signoff criteria; debug complex RTL, verification infrastructure, emulation models, firmware, and mixed-signal blocks; mentor engineers and drive verification methodology across the team.
Required Qualifications
- BS in Electrical Engineering, Computer Engineering, or related field with 12+ years of relevant ASIC/SoC verification experience
- 6+ years of hands-on experience with hardware emulation or acceleration platforms such as Synopsys ZeBu, Cadence Palladium, Siemens Veloce, or equivalent
- 12+ years of digital verification experience across complex IP, subsystem, or SoC-level designs, from verification planning through debug, coverage, and signoff closure
- Strong SystemVerilog skills; familiarity with UVM is expected
- Strong coding and automation skills using Python, Tcl, Perl, Shell, Make
- Experience with AMBA AXI/AHB/APB, PCIe, UCIe, Ethernet, SPI/I2C, memory-mapped buses; clock domains, reset domains, CDC/RDC-sensitive logic
- Experience developing verification flows, regression automation, emulation build scripts, log analysis tools, coverage reporting, dashboards, or debug utilities
- Experience with real-number models, behavioral models, mixed-signal abstraction models; use of assertions and formal techniques
- Firmware interaction and software collaboration for pre-silicon workloads and diagnostics
- Mentor engineers and drive verification methodology across the team
Desired Qualifications
- BS in Electrical Engineering, Computer Engineering, or related field with 12+ years of relevant ASIC/SoC verification experience
- 6+ years of hands-on experience with hardware emulation or acceleration platforms such as Synopsys ZeBu, Cadence Palladium, Siemens Veloce, or equivalent
- 12+ years of digital verification experience across complex IP, subsystem, or SoC-level designs, from verification planning through debug, coverage, and signoff closure
- Strong SystemVerilog skills; familiarity with UVM
- Strong coding and automation skills using Python, Tcl, Perl, Shell, Make
- Experience with AMBA AXI/AHB/APB, PCIe, UCIe, Ethernet, SPI/I2C, memory-mapped buses; clock domains, reset domains, CDC/RDC-sensitive logic
- Experience developing verification flows, regression automation, emulation build scripts, log analysis tools, coverage reporting, dashboards, or debug utilities
- Experience with real-number models, behavioral models, mixed-signal abstraction models; use of assertions and formal techniques
- Firmware interaction and software collaboration for pre-silicon workloads and diagnostics
- Mentor engineers and drive verification methodology across the team
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