Principal Engineer, Design For Test
On-siteHyderabad, Telangana, India
Hyderabad, Telangana, IndiaOn-siteFull TimeSenior LevelDoctorate Or Professional DegreeLarge
Full TimeSenior LevelDoctorate Or Professional DegreeLarge
Job Summary
Lead and implement DFT/Test architecture for complex IP and SoC designs across 3nm, 2nm, and emerging process nodes. Drive full execution from RTL through mass production readiness, including insertion, validation, STA, pattern generation, and silicon debug. Define and enhance DFT methodologies and tool flows within the M1DPx Tessent-based environment, while mentoring a team of Staff and Senior Staff engineers. Collaborate with Physical Design, timing closure, and product teams on scan chain optimization and test data management, and interface with customers and design centers for technical education and design reviews.
Required Qualifications
- Bachelor's, Master's, or PhD in Computer Science, Electrical Engineering, or related field
- 12+ years of experience
- 10+ years of direct DFT experience in the custom chip design industry
- Hands-on expertise across full DFT execution stack: Scan/MBIST/Validation/STA/IP-DFX/ATPG/Post-Silicon Bring-up and Debug
- Thorough knowledge of DFT/Test architecture solutions
- Must have led DFT architecture definition on at least 2 designs
- Strong experience with Siemens Tessent or Synopsys TestMax for DFT insertion, ATPG, and MBIST flows
- Experience with RTL and gate-level DFT flows for advanced ASIC designs
- Understanding of physical design constraints, scan chain optimization, timing closure for DFT test modes (OCC/at-speed test)
- Demonstrated prior experience leading DFT on complex ASIC SoC tape-outs
- Strong communication skills for customer-facing and cross-functional technical discussions
- Eligible to access export-controlled information as defined under applicable law
Desired Qualifications
- Master's, or PhD in Computer Science, Electrical Engineering, or related field
- 12+ years of experience
- 10+ years of direct DFT experience in the custom chip design industry
- Hands-on expertise across full DFT execution stack: Scan/MBIST/Validation/STA/IP-DFX/ATPG/Post-Silicon Bring-up and Debug
- Thorough knowledge of DFT/Test architecture solutions
- Must have led DFT architecture definition on at least 2 designs
- Strong experience with Siemens Tessent or Synopsys TestMax for DFT insertion, ATPG, and MBIST flows
- Experience with RTL and gate-level DFT flows for advanced ASIC designs
- Understanding of physical design constraints, scan chain optimization, timing closure for DFT test modes (OCC/at-speed test)
- Demonstrated prior experience leading DFT on complex ASIC SoC tape-outs
- Strong communication skills for customer-facing and cross-functional technical discussions
- Eligible to access export-controlled information as defined under applicable law
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