Principal Engineer, Design for Test (DFT)
On-site · Bengaluru, Karnataka, India
Job Summary
Principal Engineer, Design for Test (DFT) leads DFT architecture, implementation, and silicon bring-up for complex electro-optical SoCs and chiplet-based systems. Defines and drives SoC-level DFT strategy, leads scan insertion, ATPG generation, MBIST/LBIST integration, JTAG/boundary scan, and compression methodologies; develops and validates DFT constraints, timing requirements, and test modes in collaboration with RTL and Physical Design; drives fault coverage closure, pattern validation, silicon test debug, and production ramp; collaborates across ASIC, AMS, Packaging, Firmware, Validation, and Product Engineering to ensure manufacturability and production readiness; develops automated methodologies and flows to improve DFT quality and execution efficiency; mentors engineers and supports post-silicon validation, yield analysis, and manufacturing ramp; requires hands-on leadership in a fast-paced startup environment with strong cross-functional collaboration.
Required Qualifications
- BS or MS in Electrical Engineering, Computer Engineering, or related field
- 12+ years of experience in ASIC/SoC DFT implementation and silicon bring-up
- Strong expertise in: Scan architecture and scan compression, ATPG and fault coverage analysis, MBIST/LBIST methodologies, JTAG and boundary scan, At-speed testing and silicon debug and DFT signoff and manufacturing test flows
- Strong knowledge of RTL-to-GDSII ASIC development flows
- Experience with industry-standard DFT and ATPG tools
- Strong understanding of timing constraints, clocking architectures, and multi-clock domain designs
- Experience debugging silicon and supporting high-volume manufacturing
- Strong scripting and automation skills using Python, Tcl, or similar languages
- Excellent debugging, problem-solving, and cross-functional collaboration skills
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