Principal Engineer – ASIC SoC Design
On-siteHyderabad, Telangana, India
Job Summary
Own end-to-end IP and SoC development from micro-architecture through RTL compose, integration, and physical hardware assistance. Drive SoC integration, including CDC, lint, synthesis, STA, and power analysis, while defining module interfaces and system-level architecture. Collaborate closely with Architecture, Verification, FW, DFT, Synthesis, and Physical Design teams to support post-silicon debug and bring-up activities. Provide technical mentorship and participate in design and methodology reviews. This role utilizes Micron-approved AI tools to improve engineering productivity and workflow optimization while ensuring compliance with governance standards. Requires 12+ years of hands-on IP & SoC RTL design experience and strong expertise in micro-architecture, Verilog/System Verilog, and RTL integration.
Required Qualifications
- 12+ years of hands-on IP & SoC RTL design experience
- Strong expertise in micro-architecture, Verilog/System Verilog, and RTL integration
- Solid knowledge of asynchronous design concepts and CDC methodologies
- Deep understanding of SoC design flows (Lint, CDC, Synthesis/STA, Power)
- Strong fundamentals in digital design and scripting languages
- Excellent problem-solving and communication skills
- Ability to work effectively with global multi-functional teams
Desired Qualifications
- Exposure to LPDDR Subsystem, CPU Subsystems, and SoC Test Controller design
- Experience with ASIC controllers for storage or memory systems
- Hands-on post-silicon debug and silicon support experience
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