Principal Engineer, ASIC Physical Design
On-site · Bengaluru, Karnataka, India
Job Summary
The Principal Engineer, ASIC Physical Design leads end-to-end implementation of complex blocks in high-speed electro-optical SoCs, handling synthesis, place-and-route, STA, and physical verification for mixed-signal digital and analog blocks.Responsibilities include physical design of digital and custom analog/mixed-signal blocks, DFT methodology contributions, automated design flows, STA/DRC/LVS, coordinating multiple designers, and improving design implementation flows. Requires hands-on expertise in Verilog RTL, ASIC synthesis and P&R tools, timing constraints, clock tree synthesis, DFT techniques, and signoff practices. Preferred experience includes Cadence Virtuoso for manual layout, Python programming, 3DIC methodologies, SerDes knowledge, collaboration with external ASIC services, and silicon debug. Location is Bengaluru, India (on-site), with flexible hours.
Required Qualifications
- BS or MS in Electrical Engineering, Computer Engineering, or related fields
- 12+ years of work experience in ASIC physical design
- History of leading successful block implementations integrating custom IP in leading edge process nodes
- Proficient in Verilog RTL
- Mastery of ASIC synthesis (RTL Compiler, Genus, Design Compiler), place-and-route (Encounter, Innovus, ICC), and physical verification (DRC, LVS) tools and flows
- Mastery of timing constraints and deep understanding of static timing analysis
- Proficient in clock tree synthesis methodologies and customization
- Proficient in designing DFT methodologies and flows such as scan insertion, BIST, ATPG, etc.
- Proficient in ASIC signoff methodologies, checklists, and requirements
- Proficient in scripting or programming languages
- Preferred Qualifications: Working knowledge of the Cadence Virtuoso design environment for manual schematic entry and layout
- Programming experience in Python
- Experience with 3DIC implementation methodologies and custom tool flows
- Knowledge of high-speed SerDes or SerDes components
- Experience working in conjunction with external ASIC services providers
- Performed silicon debug and triage of physical design-related issues
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