Principal Engineer - ASIC DV
On-site · Bengaluru, Karnataka, India
Job Summary
Lead and drive ASIC verification efforts for IP/Block/Subsystem, including creation of verification plans, SystemVerilog/UVM testbench development, and sign-off. Mentor a team of verification engineers across global locations; ensure first-pass product quality through robust coverage and sign-off criteria. Strong hands-on expertise in Verilog/SystemVerilog, UVM, RTL debugging, and verification methodologies; familiar with AMBA AXI/AHB protocols, DDR memory-related IPs, and building comprehensive test environments. Requires 10+ years of experience and proven ability to collaborate across cross-functional teams to deliver verified IP/Block/Subsystem solutions.
Required Qualifications
- M.S./M.Tech, BS/BE (Electronics) with 10+ Years of experience
- expertise in IP/Block/Subsystem level verification
- Experience with AMBA protocols like AXI/AHB
- Proven track record of building Verification Plan, UVM Environment and Test Benches
- Experience with RTL debugging, Scoreboard, Assertions, Functional coverage coding and Code Coverage analysis
- Sound knowledge of Verilog and System Verilog languages
Apply with one swipe on Sorce. We auto-fill applications and apply on your behalf — no cover letters, no 40-minute forms.
Hiring someone like this?
Get your role in front of qualified candidates on Sorce.