Principal Engineer, ASIC Development Engineering (Front End CAD -RTL Integration, Lint, CDC)
On-site · Bengaluru, Karnataka, India
Job Summary
Lead and own front-end ASIC design methodologies and RTL integration flows for multi-million gate SoC programs, including IP stitching, HDL linting, CDC/RDC verification, ECO flows, early PPA estimation, and end-to-end flow automation. Collaborate with RTL designers, verification, synthesis, and physical design teams to drive correct-by-construction practices, shift-left verification, and tooling enhancements. Proficient in RTL design principles, linting tools, CDC/RDC verification, ECO methodologies, and PPA estimation tools; hands-on scripting (TCL, Python, Perl, Shell) and experience with industry tools (SpyGlass, HAL, Questa AutoCheck, Conformal, Fusion Compiler, Genus, etc.). Education background includes B.Tech / M.Tech / MS in related fields, with ~10 years of front-end ASIC design or methodology experience.
Required Qualifications
- B.Tech / M.Tech / MS in VLSI Design, Electrical Engineering, Computer Engineering, or a related field (or equivalent industry experience)
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