Principal Engineer, ASIC Design Verification
On-site · Bengaluru, Karnataka, India
Job Summary
Lead verification strategy for Ayar Labs' next-generation silicon photonic chip. Architect modular, reusable UVM testbenches for complex IP blocks and subsystems; set verification methodologies, coding guidelines, and coverage metrics; evaluate/implement new EDA tools, formal verification techniques, and emulation flows. Collaborate with Architects and RTL Designers to define the verification plan, identify bottlenecks, and ensure micro-architecture testability. Spearhead debugging across RTL, firmware, and the verification environment; provide technical leadership, conduct code reviews, and mentor engineers. Develop automation to run regression tests, analyze performance, and drive coverage closure.
Required Qualifications
- MS in Electrical Engineering, Computer Engineering, or related field with 12+ years of relevant experience in ASIC/SoC verification
- Expert-level proficiency in SystemVerilog and UVM (Universal Verification Methodology)
- Architecture: Proven track record of building verification environments from scratch (Agents, Scoreboards, Sequencers, etc.)
- Protocols: Deep knowledge of standard interface protocols (PCIe, ARM MCU, AMBA/AXI, UCIe)
- Scripting: Strong proficiency in scripting languages for automation (Python, Perl, Tcl, or Shell)
- Coverage: Experience defining functional coverage groups and driving logic verification to 100% closure
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