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Renesas ElectronicsPosted 2 weeks ago

Principal Digital Engineer (DFT Design)

HybridChandler, Arizona, United States

Full TimeSenior LevelEnterpriseSemiconductors

Job Summary

Insert DFT/Scan on digital logic, perform ATPG, and validate test patterns on pre and post layout gate level netlists. Deliver test patterns to the TEST engineering team, validate them on silicon, and debug scan pattern failures on ATE. Insert Logicbist using industry standard tools, improve scan coverage, and modify RTL for scan to reduce ATE tester time while meeting ASIL-B/D requirements. Participate in the full digital design flow, including RTL coding, synthesis, timing analysis, and CDC, while collaborating with architects, P&R, and silicon validation teams. Own DFT specifications, create top-level test benches, and lead design reviews to ensure compliance with automotive test standards.

Required Qualifications

  • Masters plus 12+ years or Bachelors plus 15+ years experience in digital design and DFT implementation
  • Must be a team player and yet be an independent thinker with strong digital design and DFT fundamentals
  • Hands on experience in Scan insertion, improving scan coverage, ATPG, experience in Logicbist insertion during synthesis or rtl
  • Gate level simulations with test patterns, delivering test patterns to Test engineering team and work closely with them to get the patterns validated
  • Must have basic digital RTL coding experience besides synthesis exposure
  • Must have experience with at least 8 tapeouts with hands on experience with DFT/Scan
  • Must have experience with industry standard Synopsys, Cadence, Mentor, Siemens for scan, Lbist insertion and ATPG
  • Attention to detail, accuracy and expertise in DFT required
  • Must have good written and verbal cross-functional communication skills
  • Have an analytical mind - be open to new ideas and have capability to persuade others in convincing and implementing better flows and processes
  • Working on-site for 3 days a week is a must
  • BSEE required

Desired Qualifications

  • Ideal candidate will have solid understanding of synthesizable design, timing constraints and exceptions
  • Must have experience with industry standard Synopsys, Cadence, Mentor, Siemens for scan, Lbist insertion and ATPG. Tetramax experience is a huge plus
  • Mixed signal experience highly preferred
  • Exposure to automotive test requirements, ASIL, is highly preferred
  • MSEE preferred

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