Principal Digital Design Engineer
On-site · Duluth, Georgia, United States
Job Summary
Principal Digital Design Engineer responsible for RTL design and architecture for memory data buffer chips used in data centers for AI and cloud computing. Propose, architect, and design RTL in Verilog for memory data buffers supporting DDR5/DDR6 and beyond. Collaborate within an experienced team; apply clocking controls, FSMs, low-power techniques, and high-speed design concepts. Participate in design, architecture, and verification reviews; oversee digital backend design including synthesis, static timing analysis, and logic equivalence checking. Produce documentation for design, verification, and test teams; assist with proposing, defining, documenting, and implementing new features. Mentor and train junior engineers and New College Grad engineers.
Required Qualifications
- 8+ years of direct experience in ASIC/IC design with deep knowledge of the entire IC design flow
- Fluent in Verilog RTL coding and ASIC design methodology
- Experience with static timing analysis and creation of place and route constraints
- Proficiency in formal verification, linting, and CDC/RDC checking
- Knowledge of asynchronous clock crossings and synthesis implications of RTL
- Experience implementing and verifying ECOs on RTL, synthesized, and post-route netlists
- Experience with gate-level simulations and understanding the causes and implications of timing violations
- Experience with DFT or physical design (a plus)
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
- 12+ years of experience in ASIC/IC design
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