Principal Digital Design Engineer
$185,000–$230,000 year
On-site · San Jose, California, United States
San Jose, California, United StatesOn-siteFull Time$185,000–$230,000 yearSenior LevelBachelors DegreeSemiconductorsUnknown
Type
Full Time
Level
Senior Level
Education
Bachelors Degree
Company size
Unknown
Industry
Semiconductors
Job Summary
Principal Digital Design Engineer at Astera Labs focusing on front-end circuit design for high-performance network controllers with expertise in RTL, Synthesis, IP integration, and block-level verification across PCIe, Ethernet, Infiniband, DDR, NVMe, and USB; responsibilities include architecture-to-production ownership, DFT, UVM verification, and silicon bring-up in a 28nm CMOS process; base salary range is $185k-$230k with US work authorization.
Required Qualifications
- Bachelor’s degree in Electrical Engineering (EE) required; Master’s preferred
- +8 years’ experience in complex SoC/silicon development for Server/Storage/Networking
- Strong knowledge of high-speed protocols (PCIe Gen-3+, Ethernet, Infiniband, DDR, NVMe, USB)
- Experience with front-end design (architecture, RTL, simulations, synthesis, timing closure, DFT)
- Full chip or block-level ownership from architecture to GDS
- Experience with Synopsys and/or Cadence flows
- DFT and transition test knowledge
- UVM-based design verification
- Silicon bring-up and debug expertise
- Small-geometry CMOS (≤28nm) design
- Authorized to work in the US
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