Principal Digital Design Engineer
On-site · San Jose, California, United States
Job Summary
Lead digital design blocks for high-speed SerDes in AI systems. Define architecture, code and deliver RTL to PD and DV teams, and collaborate with the DSP Architecture team to optimize power, latency, and performance. Drive full design cycle responsibilities from micro-architecture to tapeout, addressing timing fixes, area and power optimizations, and silicon issues. Focus on 100G+ PAM4 DSP SerDes, with experience in PAM4 DSP blocks for FFE/DFE/MLSD and digital timing recovery. Work with PD/DV teams to resolve timing, CDC, and lint issues and push for high-quality RTL delivery.
Required Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
- 5-10 years of experience in digital design for high-speed DSP data path
- Proficiency in coding System Verilog for complex design blocks
- Experience with EDA tools for Synthesis, Lint, CDC, and Prime Time
- Experience taking design blocks through full design cycle from micro-architecture to tapeout
- Experience with timing fixes, area and power optimizations, and resolving silicon issues
- Serve as responsible engineer for at least one critical design block including architecture definition, design specifications, and RTL delivery
- Code and deliver high-quality RTL to PD and DV teams
- Collaborate with DSP Architecture team to define new features and optimizations for power, latency, and performance
- Work with PD team to resolve timing violations, Spyglass warnings/errors, and CDC violations
- Partner with DV team to root-cause and fix design bugs
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