Principal DFT Engineer, HBM
$146,000–$309,000 year
On-siteFolsom, California, United States
Job Summary
Own SoC-level DFT implementation, including scan, MBIST, LBIST, boundary scan, and test access architectures for HBM base-die designs. Drive DFT architecture definition early in the design cycle, ensuring alignment with SoC integration, floor planning, timing, power, and physical design constraints. Implement and integrate DFT logic at the block, subsystem, and full-chip levels while owning flow execution and signoff, including lint, CDC, rule checks, ATPG readiness, and coverage closure. Collaborate with physical design, verification, and manufacturing teams to optimize solutions for placement, routing, and yield. Support pre-silicon debug and post-silicon bring-up analysis. Partner with CAD teams to standardize DFT flows across HBM SoC programs.
Required Qualifications
- Bachelor's degree or higher in Electrical Engineering, Computer Engineering, or related field
- 7+ years of relevant experience in SoC design, DFT, or implementation for complex digital ASICs or SoCs
- Experience with scan insertion, MBIST/LBIST architectures, JTAG/boundary scan, and ATPG concepts
- Familiarity with full RTL-to-GDS SoC flows, including interaction between DFT, synthesis, STA, and physical design
- Experience working with large, complex SoCs involving multiple IPs and subsystems
- Proficiency with industry-standard EDA tools from Siemens, Synopsys, and/or Cadence for DFT and implementation
- Familiarity with scripting languages (Python, Tcl, Perl, etc.) for flow automation
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