Principal Design Verification Engineer- SerDes/PHY
$207,000–$230,000 year
On-siteSan Jose, California, United States
Job Summary
Architect UVM-based verification environments for SerDes/PHY IP, including PMA, PCS, and PHY-MAC interface layers. Develop SystemVerilog/UVM testbenches, sequences, and scoreboards for multi-Gbps SerDes lanes, executing functional, performance, and corner-case verification across equalization, CDR, training, and link bring-up scenarios. Lead coverage analysis and closure, debug failures with designers, and drive regressions to clean tape-out. Verify PHY behavior against industry specifications including PCIe Gen 6/Gen 7, UALink, UCIe, and Ethernet standards while partnering with analog/AMS designers on Real Number Modeling. Mentor junior DV engineers and set technical direction across the verification team.
Required Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
- 8+ years of design verification experience on high-speed SerDes, PHY, or mixed-signal IP
- Strong understanding of the physical layer, including equalization (CTLE, DFE, FFE), CDR, training sequences, and link bring-up
- Expert-level proficiency in SystemVerilog and UVM
- Hands-on experience with analog/mixed-signal co-simulation and Real Number Modeling (RNM)
- Working knowledge of one or more high-speed serial protocols: PCIe, UALink, UCIe, Ethernet, or CXL
Desired Qualifications
- MS or PhD in Electrical Engineering or Computer Engineering
- Experience verifying PCIe Gen 6/Gen 7, UALink, or UCIe SerDes/PHY IP
- Familiarity with emulation platforms (Palladium, Veloce, or ZeBu) and gate-level simulation flows
- Scripting proficiency in Python or Perl for verification automation and regression management
- Experience supporting post-silicon bring-up and correlating pre-silicon coverage with silicon results
- Proven ability to lead technically across a multi-disciplinary team in a fast-paced environment
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