Principal Design Verification Engineer
$180,000–$255,000 year
On-siteSan Jose, California, United States
Job Summary
Own verification end to end for a major subsystem of the RDU, including test plan, testbench architecture, coverage model, and sign-off criteria. Build the coverage model, drive it to closure ahead of tape-out, and develop testbench components, agents, checkers, and stimulus at block, full-chip, system, and gate levels. Serve as the technical authority by reviewing testbench design decisions, leading debug on hardest failures, and driving root cause analysis for regression health. Verify functional and performance behavior against production ML workloads, while advancing DV methodology through reusable infrastructure and AI-assisted workflows. Contribute to emulation and FPGA prototyping, support silicon bring-up, and mentor engineers to raise team standards.
Required Qualifications
- BS or MS in EE, CS, or CE
- 7+ years (or equivalent) of industry experience in ASIC design verification
- Deep hands-on expertise in SystemVerilog
- Deep hands-on expertise in SVA
- Standard methodology (UVM, OVM, or VMM)
- Scripting in Python
- Scripting in C/C++
- Full-cycle DV ownership from test plan through tape-out
- Owning a coverage model to closure
- Experience verifying digital logic in a CPU
- Experience verifying digital logic in a GPU
- Experience verifying digital logic in a SoC
- Experience verifying digital logic in a comparably complex ASIC
- Track record of debugging hard, intermittent, or low-reproducibility pre-silicon failures to root cause
- Demonstrated technical leadership without formal authority
- Setting direction in reviews
- Arbitrating testbench decisions
- Mentoring engineers
- Working knowledge of modern computer architecture
- Working knowledge of machine learning accelerators or SoCs
Desired Qualifications
- MS or PhD in EE, CS, or CE
- 10+ years of experience in ASIC design verification
- Depth in high-speed I/O verification
- Protocol-level verification of PCIe
- Protocol-level verification of Ethernet
- Memory subsystems such as HBM or DDR
- Performance verification methodology
- Building performance benches
- Analyzing results
- Functional correctness
- Formal verification
- Assertion-based methods
- Experience evaluating, integrating, and validating third-party verification IP
- Gate-level simulation
- Gate-level debug
- Emulation and FPGA prototyping platforms
- Post-silicon lab bring-up
- Functional validation
- Debugging first-silicon issues to root cause
- Strong understanding of computation
- Strong understanding of interconnect
- Strong understanding of memory systems
- Fluency with Claude
- Fluency with other AI tools
- AI tools applied to verification
- AI tools applied to flow development
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