Principal Design Engineer
On-site · Bengaluru, Karnataka, India
Job Summary
Lead PCIe design efforts for high-speed interface IPs at Cadence. Drive design and micro-architecture with hands-on expertise, optimize performance, power, and area (PPA), and collaborate with DV teams to resolve design issues. Strong scripting skills and experience applying AI-assisted design tools in the development flow are required. Desired experience includes integrity and data encryption (AES, GCM) and Automotive/FuSa exposure. Education: B.Tech / M.Tech in Electronics, Electrical, or Computer Science.
Required Qualifications
- B.Tech / M.Tech in Electronics, Electrical, or Computer Science
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