Principal ASIC Engineer (Reliability & Hardware Validation) Hybrid
$231,400–$331,800 year
HybridSan Jose, California, United States
Job Summary
Define and execute comprehensive product qualification plans for next-generation, high-power solutions, driving robust HTOL, burn-in, and stress testing while managing reliability suppliers. Lead hardware design, schematic generation, and validation for service provider routing products, overseeing board bring-up and debug processes. Conduct failure analysis activities to generate detailed qualification reports and partner with eCAD, FPGA, and signal integrity teams to support design-for-reliability. Provide technical documentation and support for customer quality and reliability requirements. This role bridges semiconductor reliability testing with high-speed hardware board design for Cisco's next-generation networking products in a hybrid San Jose environment.
Required Qualifications
- Master's degree in electrical engineering, Computer Engineering, or a related field
- 10+ years of professional experience in semiconductor reliability and/or high-speed hardware design
- Proven experience in developing high-power HTOL/Burn-In testing for advanced node products
- Deep knowledge of JEDEC, AEC, and Telcordia standards
- Hands-on experience with high-speed network interfaces, board design, and familiarity with tools such as Cadence Allegro
- Experience with high-speed measurement equipment and automated test development
- Ability to interpret sophisticated schematics and layouts
- Proficiency in data analysis/debug and HTOL set-up
Desired Qualifications
- PhD in Electrical or Computer Engineering
- Experience with 2nm/3nm Hyperscaler Multi-Chip-Modules and advanced packaging (CoWoS, SoIC, EMIB)
- Deep expertise in >100Gbps system design, signal integrity, and power distribution
- Knowledge of SerDes architecture (NRZ/PAM4 at 56G/112G/224G+), PCIe Gen5/6, and 800G Ethernet
- Proficiency in Python, Perl, TCL, or Verilog for scripting and automation
- Experience with JMP, Reliasoft, or Minitab for reliability statistical analysis
- Understanding of FMEA processes, risk assessment, and reliability lifetime modeling
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