Principal ASIC Design Engineer (Starshield)

Principal ASIC Design Engineer (Starshield): Lead digital ASIC/FPGA development for Starshield programs focused on government use, collaborating across hardware/software boundaries. Design RTL in Verilog/SystemVerilog, define micro-architecture, meet timing and synthesis goals, and work with verification teams to ensure full coverage. Participate in silicon bring-up and validation, and assist in developing automated test lab equipment for measurements. Must have a bachelor’s degree in EE/CE/CS and 10+ years of RTL/FPGA/ASIC experience; familiarity with clock-domain crossings, power optimization, multicore CPU subsystems, standard bus protocols (AXI/AHB), embedded processors, high-speed/low-power design techniques, and EDA tools (VCS, Questa, IES, Vivado, Quartus). Additional requirements include willingness to travel for off-site testing and the possibility of TS-SCI clearance. ITAR compliance and strong teamwork are emphasized. Compensation range: $210,000–$295,000 per year, plus incentives and comprehensive benefits.