Principal ASIC Design Engineer
$145,800–$194,400 year
On-siteOttawa, Ontario, Canada
Job Summary
Define and implement front-end methodologies for synthesis, static timing analysis, and clock/reset domain crossing. Develop flows enabling early detection of physical design and timing challenges to ensure efficient handoff to back-end teams. Collaborate with Architecture, RTL, Physical Design, Timing, and DFT teams to drive seamless integration throughout the SoC development lifecycle. Drive delivery of complex, high-performance, timing-critical designs across all phases of the front-end design flow, including timing closure and power optimization. Establish EDA methodologies for front-end design to ensure design intent is accurately reflected through robust constraints and implementation strategies.
Required Qualifications
- Bachelor's degree in computer science, Electrical Engineering, or a related field
- 10–20 years of relevant industry experience
- Master's/PhD in a related field
- 8–20 years of experience (for Master's/PhD holders)
- Strong foundation in ASIC design, verification, architecture, and front-end design methodologies
- Solid understanding of ASIC back-end design, EDA tools, and associated design methodologies
- Hands-on experience with SoC architecture, including processor cores, memory subsystems, and peripheral interfaces
- Extensive experience with Verilog/SystemVerilog
- Experience with linting
- Experience with synthesis
- Experience with static timing analysis
- Experience with clock and reset domain crossing (CDC/RDC)
- Experience with formal equivalence checking between RTL and gate-level netlists
- Proficiency in scripting and automation using languages such as Python or Perl
- Demonstrated track record of delivering production-quality silicon on aggressive development timelines
Desired Qualifications
- Experience with high-speed protocol domains such as Ethernet, PCIe, and emerging standards (e.g., UALink)
- Familiarity with applying AI/ML techniques to ASIC development
- Experience designing, verifying, and testing high-speed datapath logic
- Expertise working with large datapath FPGAs and advanced ASIC technology nodes
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