Power Integrity Engineer-Silicon
On-site · San Jose, California, United States
Job Summary
Senior/Principal Power Integrity Engineer to own and drive power delivery strategies across 2.5D/3D packages that integrate electrical ICs, photonic ICs, chiplets, and high-bandwidth memory. Architect robust, low-noise, high-efficiency PDNs, define PI architectures, perform full-stack PI analysis from die-level IR drop to package-level PDN impedance, model and validate solutions with tools (Ansys SIwave, HFSS, Cadence Sigrity, Apache RedHawk, Voltus, etc.), lead PI co-design with silicon, package, and photonics teams, qualify PDN components, collaborate with foundry/OSAT partners, develop methodologies and sign-off criteria, analyze reliability risks (EM, TDDB, thermal effects), and drive readiness for volume production in high-performance AI accelerators and photonic interconnects.
Required Qualifications
- Bachelor’s degree in Electrical Engineering, Physics, or related field plus 10+ years of relevant industry experience; or Master’s/PhD plus 7+ years of related experience.
- Hands-on proficiency with PI simulation tools (e.g., Ansys, Cadence/Sigrity, Keysight ADS, Apache/RedHawk, Voltus or equivalents).
- Experience leading complex cross-functional programs across global teams, foundries, OSATs, and suppliers.
- Strong understanding of PDN design principles, IR drop/EM analysis, on-chip/off-chip decoupling, high-speed signaling, and noise mitigation for AI/HPC workloads.
- Ability to lead power integrity efforts in advanced packaging environments (2.5D/3D, chiplets, silicon interposers/bridges, CoWoS, or similar).
- Excellent communication, presentation, and documentation skills to influence stakeholders.
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