Post silicon validation engineer
$108,000–$172,800 year
On-site · Austin, Texas, United States
Job Summary
Post-silicon validation engineer to drive bring-up, characterization, and debugging of Ethernet and PCIe Retimer chips. Role focuses on advanced Ethernet PHY validation to meet IEEE networking standards and high-speed interoperability. Key duties include hands-on multi-rate Retimer IC bring-up, validating Ethernet (100G/400G/800G) and PCIe (Gen5/6) for IEEE and PCI-SIG compliance, and building Python-based automated test frameworks for Ethernet throughput, BER, and control-path testing using ARM micros and GPIO/MDIO/I2C protocols. Perform root-cause analysis of silicon, link training, and firmware bugs with protocol analyzers and traffic generators. Required expertise includes Ethernet PHY architecture, PAM4/NRZ signaling, FEC, Auto-Negotiation, Link Training, lab equipment (high-bandwidth oscilloscopes, BERTs, Ethernet traffic generators like Ixia/Spirent, PCIe analyzers), and programming skills in Python for automation plus C/C++ for low-level register manipulation. Education: Bachelors in Engineering with 8+ years of related experience or Masters in Engineering with 6+ years of related experience. Compensation includes base salary $108,000-$172,800 plus discretionary bonus and equity; comprehensive benefits; equal opportunity employer.
Apply with one swipe on Sorce. We auto-fill applications and apply on your behalf — no cover letters, no 40-minute forms.
Hiring someone like this?
Get your role in front of qualified candidates on Sorce.